In general, flash memories have the advantage of not losing stored data even if power is cut, such that they are widely used for storing data for a PC Bios, a set-top box, a printer, and a network server, etc., and recently, also used in digital cameras and mobile phones. In these flash memories, EEPROM type flash memory devices, which have a function of electrically erasing data of memory cells in a package or a sector unit, increases threshold voltage of a cell transistor by generating channel hot electrons at a drain in programming and accumulating the electrons in a floating gate. On the contrary, they decrease the threshold voltage of the cell transistor by generating high voltage between a source/substrate and the floating gate to discharging the electrons accumulated in the floating gate. These EEPROM devices can be categorized as a single poly EEPROM and a double poly EEPROM, in accordance with the manufacturing technology and the number of polysilicon layers utilized.
FIG. 1 is a view showing a related single poly EEPROM and FIG. 2 is a cross-sectional view of the single poly EEPROM of FIG. 1. A single poly EEPROM is largely composed of a tunneling region A, a read transistor B, and a control gate C, etc. In order not to perform operations of programming and erasing, the EEPROM requires a large amount of capacitance ratio between the tunneling region A and the control gate C, and it is required to apply a relatively large voltage to the tunneling region A and a relatively small voltage to the control gate C to achieve the capacity difference.
The overlap area of a polysilicon layer on the tunneling region A and the control gate C may be made different to achieve the capacity difference. However, this method which can result in making the control gate C, which needs to have a relatively large area, have a relatively large area on semiconductor substrate, and as a result, the integration of the single poly EEPROM is reduced.
FIG. 3 is a simple circuit diagram of a related single poly EEPROM, in which the single poly EEPROM makes the overlap area of a polysilicon layer and an active region in the tunneling region A and the control gate C different so that the capacities are different in the two regions. In two series capacitors C1 and C2, the areas A1 and A2 are different and the capacities C1 and C2 are correspondingly different, and external bias voltage Vc for programming and erasing is divided in an inversely proportional ratio to each capacity and applied to the capacitors C1 and C2. Accordingly, the capacitor C1 having small capacity (e.g. small area) is applied with a relatively higher voltage than the capacitor C2, thereby generating tunneling. That is, the two capacitors C1 and C2 have relationships of C1=ε(A1/d), C2=ε(A2/d), C1/C2=A1/A2=V2/V1, etc.
In the structure of the single poly EEPROM, since there may be a ratio of the overlap area difference so that tunneling is generated at a side and not generated at the other side, the control gate C that is a region where tunneling should not be generated has to have a relatively large area. For example, there may be several tens of times difference between the areas (i.e., a and c) of the polysilicon overlapping at the tunneling region A and the region of the control gate C; therefore, the area of the control gate C occupies a relatively large portion of the area of the single poly EEPROM, which reduces the integration of the single poly EEPROM.